• DocumentCode
    2123059
  • Title

    Multilevel logic synthesis of very high complexity circuits

  • Author

    Burgun, L. ; Dictus, N. ; Greiner, A. ; Pradho, E. ; Sarwary, C.

  • Author_Institution
    Lab. MASI/CAO-VLSI, Univ. Pierre et Marie Curie, Paris, France
  • fYear
    1994
  • fDate
    28 Feb-3 Mar 1994
  • Firstpage
    669
  • Abstract
    This paper presents an approach based on ROBDD representation for multilevel logic synthesis. This approach makes it possible to handle very high complexity circuits that cannot be synthesized by the classical factorization algorithms. Two important algorithms are used. The former generates a multilevel expression from an ROBDD. The latter builds a minimal ROBDD from the two ROBDDs representing an incompletely specified Boolean function. This approach is implemented in the logic synthesis software LOGIC developed as part of the ALLIANCE CAD package
  • Keywords
    Boolean functions; logic CAD; many-valued logics; ALLIANCE CAD package; LOGIC; ROBDD representation; binary decision diagrams; high complexity circuits; incompletely specified Boolean function; logic synthesis software; multilevel logic synthesis; Boolean functions; Circuit synthesis; Data structures; Delay; Libraries; Logic circuits; Logic design; Network synthesis; Packaging; Software packages;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-5410-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1994.326795
  • Filename
    326795