DocumentCode
2123082
Title
A redefinable symbolic simulation technique for testability design rules checking
Author
Hirech, M. ; Floret, O. ; Greiner, A. ; Rejouan, E.
Author_Institution
Lab. MASI/CAO-VLSI, Univ. Pierre et Marie Curie, Paris, France
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
668
Abstract
A new symbolic simulation technique for design for testability (DFT) rules checking is discussed. With this method symbolic values and transfer functions of gates are redefinable to allow an adaptability to different sets of rules
Keywords
circuit analysis computing; design for testability; logic CAD; logic testing; transfer functions; DFT rules checking; design for testability; redefinable simulation technique; symbolic simulation technique; symbolic values; testability design rules checking; transfer functions; Circuit simulation; Circuit testing; Design for testability; Latches; Logic circuits; Logic gates; Merging; Phase detection; Registers; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326796
Filename
326796
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