A novel CMOS edge equalizer for 10-GB/S highly lossy backplane

This paper presents a novel CMOS edge equalizer for 10-Gb/s transceivers for backplane channels with high loss. The equalizer reduces ISI at edges and ISI at data centers simultaneously without incurring multilevel detection. Unlike conventional edge equalizer that recovers data from current sample and previous sample, this equalizer recovers data only from current sample so that error propagation is avoided. It requires much less high-frequency boost while maintaining the amenity for CMOS implementation of conventional CMOS feed-forward-equalizer. The equalizer is implemented in TSMC 90-nm CMOS technologies. Comparison shows for highly lossy backplane applications, it is superior to decision-feed-back-equalizer, linear-feed-forward-equalizer, and conventional edge equalizer.