Title :
Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits
Author :
Abderrahman, A. ; Kaminska, B. ; Savaria, Y.
Author_Institution :
Dept. of Electr. and Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
fDate :
28 Feb-3 Mar 1994
Abstract :
Digital and mixed circuits performance are affected and limited by the simultaneous switching power and ground noise. For accurately selecting the number of power/ground pins to overcome switching noise, it is very important to accurately estimate the worst case simultaneous switching power and ground noise. In this paper we propose a heuristic that helps to estimate this worst case
Keywords :
CMOS integrated circuits; combinatorial circuits; integrated logic circuits; semiconductor device noise; switching; logic IC; logic circuits; power/ground pins number selection; simultaneous switching noise; static CMOS combinational circuits; switching ground noise; switching power noise; worst case estimation; Binary decision diagrams; Circuit noise; Circuit simulation; Combinational circuits; Data structures; Delay; Driver circuits; Logic circuits; Switches; Switching circuits;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326804
