DocumentCode
2123455
Title
Clean formal semantics for VHDL
Author
Breuer, Peter T. ; Fernández, Luis Sanchez ; Kloos, Carlos Delgado
Author_Institution
ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
641
Lastpage
647
Abstract
A simple formal semantics for the standard hardware description language VHDL is set out in functional style. The presentation comprises an executable specification for a synchronously clocked VHDL simulator
Keywords
VLSI; circuit CAD; circuit analysis computing; digital integrated circuits; specification languages; VHDL; VHSIC HDL; digital VLSI circuits; formal semantics; hardware description language; synchronously clocked VHDL simulator; Clocks; Functional programming; Hardware design languages; Humans; Kernel; Libraries; Natural languages; Signal processing; Standards development; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326810
Filename
326810
Link To Document