Title :
Challenges of designing electrostatic discharge (ESD) protection in modern and emerging CMOS technologies
Author_Institution :
Univ. of Central Florida, Orlando, FL, USA
Abstract :
Electrostatic discharge (ESD) induced failures continue to be a major reliability concern in the semiconductor industry. Such a concern will in fact be intensified as the CMOS technology is scaling toward the 22-nm and beyond. This paper covers the issues and challenges pertinent to the design of electrostatic discharge (ESD) protection solutions of modern and future CMOS integrated circuits, including the high-voltage, low-voltage, and emerging nanowire technologies.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; low-power electronics; nanoelectronics; nanowires; CMOS technology; ESD; electrostatic discharge induced failures; electrostatic discharge protection; nanowire technology; semiconductor industry; size 22 nm; CMOS integrated circuits; CMOS technology; Discharges (electric); Electrostatic discharges; Next generation networking; Silicon;
Conference_Titel :
Next-Generation Electronics (ISNE), 2013 IEEE International Symposium on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4673-3036-7
DOI :
10.1109/ISNE.2013.6512271
