Variable accuracy device modeling for event-driven circuit simulation

Author

Michaels, Kimon W. ; Strojwas, Andrzej J.

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

557

Lastpage

561

Abstract

This paper presents a complete variable accuracy device modeling methodology which varies the error tolerances and device model accuracy during the simulation based upon the dynamic state of operation of the circuit and the circuit topology. The number of device model evaluations required and the average device model evaluation time are minimized

Keywords

SPICE; circuit analysis computing; discrete event simulation; network topology; semiconductor device models; BJT; BSIM model; MOSFET; SPICE level 1 model; circuit dynamic operation state; circuit topology; device model accuracy; error tolerance; event-driven circuit simulation; maximum required model complexity; timing error; variable accuracy device modeling methodology; Circuit simulation; Circuit topology; Computational modeling; Computer errors; Computer simulation; Discrete event simulation; Error analysis; Surfaces; Timing; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326819

Filename

326819