Logic and fault simulation by cellular automata

Author

Li, Yih-Lang ; Wu, Cheng-Wen

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

552

Lastpage

556

Abstract

We propose a massively parallel architecture to speed up logic and fault simulation. We use 2-D cellular automata (CA) to implement the logic and fault simulation of combinational circuits. Our CA has six cell states, and operates in a pipelined fashion. Experimental results on ISCAS85 benchmark circuits show that our CA outperforms previously reported parallel simulators. As to pure logic simulation, our CA performs up to 9.24 billion GEPS using a 20 MHz clock and 8-bit words as opposed to 5 billion GEPS

Keywords

cellular automata; circuit analysis computing; combinatorial circuits; logic CAD; logic testing; parallel architectures; pipeline processing; 2D cellular automata; C language implementation; ISCAS85 benchmark circuits; acyclic digraph; combinational circuits; fault simulation; graph embedding; logic simulation; massively parallel architecture; pipelined operation; Circuit faults; Circuit simulation; Clocks; Combinational circuits; Computational modeling; Costs; Logic circuits; Logic design; Parallel processing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326820

Filename

326820