A reduced-swing data transmission scheme for resistive bus lines in VLSIs

Author

Ikeda, M. ; Asada, K.

Author_Institution

Dept. of Electr. Eng., Tokyo Univ., Japan

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

546

Lastpage

550

Abstract

An optimal design method of on-chip communication circuits is presented, where a reducing signal swing scheme is employed using termination resistors and sense amplifiers. Although this method treats distributed capacitance and resistance in bus lines as lumped elements, it is demonstrated that the error introduced is small. With an optimum circuit designed by this method, a low power design compared with the conventional buffer-chained circuit is realized without changing system level design in the ASIC as well

Keywords

CMOS integrated circuits; application specific integrated circuits; data communication equipment; lumped parameter networks; microprocessor chips; semiconductor-insulator boundaries; silicon; ASIC; SOI technology; VLSI bus architecture; circuit model; circuit optimization; data transmission scheme; low power design; lumped elements; on-chip communication circuits; optimal design method; reducing signal swing scheme; resistive bus lines; sense amplifiers; termination resistors; Capacitance; Data communication; Delay effects; Design optimization; Driver circuits; Equivalent circuits; Inverters; Resistors; SPICE; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326821

Filename

326821