DocumentCode
2123708
Title
A global router on GPU architecture
Author
Yiding Han ; Chakraborty, Koushik ; Roy, Sandip
Author_Institution
Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA
fYear
2013
fDate
6-9 Oct. 2013
Firstpage
78
Lastpage
84
Abstract
In the modern VLSI design flow, global router is often utilized to provide fast and accurate congestion analysis for upstream processes to improve the design routability. Global routing parallelization is a good candidate to speedup its runtime performance while delivering very competitive solution quality. In this paper, we first study the cause of insufficient exploitable concurrency of the existing net level concurrency model, which has become a major bottleneck for parallelizing the emerging design problems. Then, we mitigate this limitation with a novel fine grain parallel model, with which a GPU based multi-agent global router is designed. Our experimental results indicate that the parallel model can effectively support the GPU based global router, and deliver stable solutions. The runtime comparison with NCTUgr2 has shown that upto 3.9× speedup is achieved by the GPU based router.
Keywords
VLSI; concurrency theory; graphics processing units; integrated circuit design; network routing; GPU architecture; NCTUgr2; VLSI design flow; fine grain parallel model; global router; net level concurrency model; Benchmark testing; Concurrent computing; Degradation; Graphics processing units; Memory management; Routing; Topology; A* search; GPGPU; Global Routing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2013 IEEE 31st International Conference on
Conference_Location
Asheville, NC
Type
conf
DOI
10.1109/ICCD.2013.6657028
Filename
6657028
Link To Document