Optimal design of video decoder based on PowerPC 405

In order to improve the comprehensive performance of portable media player video decoding, adopts the mpeg-4 video decoder in software and hardware co-design. Through the division of software and hardware, the study is the IP core optimized design and implementation in two-dimensional inverse discrete cosine transform, motion compensation, color space conversion. It builds a video decoding model of hardware and software co-design based on hard-core PowerPC 405. As the core for Xilinx FPGA chip, the study builds SOPC test. The results show that the CIF video sequences are supported the real-time decoding at the operating frequency only 100 MHz. This system achieves real-time video playback in low power consumption, high reliability and flexibility.