Title :
Efficient path identification for delay testing - time and space optimization
Author :
Wittman, H. ; Henftling, Manfred
Author_Institution :
Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
fDate :
28 Feb-3 Mar 1994
Abstract :
This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per path. Compared to former approaches, experimental results show fast access, small memory requirements, and negligible CPU-times for the management of huge path sets
Keywords :
automatic testing; circuit analysis computing; delays; integrated circuit testing; integrated logic circuits; logic testing; delay testing; logic ICs; path identification; path-delay fault testing; space optimization; time optimization; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Delay effects; Design optimization; Electronic equipment testing; Logic testing; Semiconductor device modeling; System testing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326827
