Via-configurable structured ASIC implementation of OpenRISC 1200 based SoC platform

Structured ASIC technology improves manufacturing yield and reduces manufacturing turnaround time with a low NRE cost. In this paper we present an implementation of an OR1200-based SOC platform using our structured ASIC technology. Our structured ASIC technology features a via-configurable logic block used to implement both combinational and sequential logic gates. It is accompanied by a library and chip design methodology based on existing standard cell design tools. Our structured ASIC implementation can achieve an operating frequency of 90 MHz with a 0.18um process technology. Such an operating frequency is comparable to that of its counterpart implemented using a commercial standard cell library.