DocumentCode
2123903
Title
A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip
Author
Watanabe, T. ; Fujita, R. ; Yanagisawa, K. ; Tanaka, H. ; Ayukawa, K. ; Soga, M. ; Tanaka, Y. ; Sugie, Y. ; Nakagome, Y.
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fYear
1996
fDate
13-15 June 1996
Firstpage
42
Lastpage
43
Abstract
Develops a modular architecture for a DRAM-integrated, multimedia chip, or media chip with a data transfer rate of 6 to 12 Gbyte/s. The DRAM macro enables the design flexibility both for DRAM capacity and the logic-memory interface to meet a wide variety of applications. A 6.4-Gbyte/s. 8-Mbit test chip was fabricated.
Keywords
DRAM chips; VLSI; cellular arrays; integrated circuit design; memory architecture; multimedia systems; 6.4 GB/s; 8 Mbit; DRAM macro; DRAM-integrated chip; VLSI; data transfer rate; design flexibility; logic-memory interface; media chip; modular architecture; multimedia chip; Random access memory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507709
Filename
507709
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