Rationale for a 3D heterogeneous multi-core processor

Author

Rotenberg, Eric ; Dwiel, Brandon H. ; Forbes, Elliott ; Zhenqian Zhang ; Widialaksono, Randy ; Basu Roy Chowdhury, Rangeen ; Tshibangu, Nyunyi ; Lipa, Steve ; Davis, William Rhett ; Franzon, Paul D.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

2013

fDate

6-9 Oct. 2013

Firstpage

154

Lastpage

168

Abstract

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.

Keywords

DRAM chips; electronic design automation; logic design; multiprocessing systems; three-dimensional integrated circuits; 2D layout; 3D die stacking; 3D heterogeneous multicore processor; L2 DRAM cache; cache-core decoupling; design automation; face-to-back, based buses; fast thread migration; frequent thread migrations; logic design; microarchitectural state; microbump based buses; physical design; plug-and-play composition; post-silicon validation; power management unit; product customization strategy; product strategy; through-silicon-via based buses; Charge coupled devices; Microarchitecture; Multicore processing; Pipelines; Registers; Software; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design (ICCD), 2013 IEEE 31st International Conference on

Conference_Location

Asheville, NC

Type

conf

DOI

10.1109/ICCD.2013.6657038

Filename

6657038