Title :
A system-design methodology: executable-specification refinement
Author :
Gajski, Daniel D. ; Vahid, Frank ; Narayan, Sanjiv
Author_Institution :
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement that result in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice
Keywords :
circuit CAD; digital integrated circuits; logic CAD; SpecSyn environment; chip-level design; executable-specification refinement; system-design methodology; system-level specification; Code standards; Computer science; Hardware; Logic; Manuals; Protocols; Software prototyping; Software standards; System-level design; Timing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326836
