• DocumentCode
    2124066
  • Title

    Scattered superpage: A case for bridging the gap between superpage and page coloring

  • Author

    Licheng Chen ; Yanan Wang ; Zehan Cui ; Yongbing Huang ; Yungang Bao ; Mingyu Chen

  • Author_Institution
    State Key Lab. of Comput. Archit., Inst. of Comput. Technol., Beijing, China
  • fYear
    2013
  • fDate
    6-9 Oct. 2013
  • Firstpage
    177
  • Lastpage
    184
  • Abstract
    Superpage and page coloring are two important practical techniques to improve the performance of Translation Lookaside Buffers (TLBs) and shared Last Level Cache (LLC) respectively. However, there exists a gap between these two techniques in current hardware-architecture design, resulting in the contradiction in adopting these two optimizations simultaneously: a superpage requires hundreds of contiguous (e.g. a power of two) base pages in both virtual and physical memory, which would compulsorily occupy all available page colors (or cache sets), thus making page coloring failed to work. This is because most contemporary architecture adopts the design with cache set indexes placed in the least significant part of block address. In this paper, we propose a lightweight approach named Scattered Superpage to bridge this gap. Scattered Superpage decouples a superpage from the limitation of occupying multiple contiguous physical base pages. A superpage is still contiguous in virtual memory, but it is scattered mapping into multiple physical superpages, and it just occupies specified partial page colors in each physical superpage, thus it allows us to configure page color for each superpage. The huge TLB is slightly modified to store page color configuration for each superpage and to calculate target physical address based on this configuration when doing address translation. The experimental results show that the Scattered Superpage can improve system performance by 20.51% and reduce unfairness by 27.77% in our 4-core simulation system (with multi-program memory-intensive workloads). It achieves this by reducing last level cache miss by 17.05% and reducing TLB miss by 86.02% simultaneously.
  • Keywords
    cache storage; multiprocessing systems; storage allocation; 4-core simulation system; LLC; TLB performance; address translation; block address; cache set index; hardware-architecture design; last level cache; multiple contiguous physical base pages; multiprogram memory-intensive workload; optimization; page color configuration; page coloring; physical address; physical memory; scattered superpage; superpage decoupling; translation lookaside buffer performance; unfairness reduction; virtual memory; Benchmark testing; Color; Hidden Markov models; Image color analysis; Indexes; Optimization; System performance; Last Level Cache; Page Coloring; Scattered Superpage; TLB;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design (ICCD), 2013 IEEE 31st International Conference on
  • Conference_Location
    Asheville, NC
  • Type

    conf

  • DOI
    10.1109/ICCD.2013.6657040
  • Filename
    6657040