Title :
A fully integrated Phase-locked loop with leakage current compensation in 65-nm CMOS technology
Author :
Se-Chun Park ; Seung-Baek Park ; Soo-won Kim
Author_Institution :
SK Hynix, South Korea
Abstract :
In this study, a fully integrated Phase-locked loop (PLL) that is applicable to Universal Flash Storage (UFS) systems is presented. The fully integrated PLL is realized using a MOS capacitor as an on-chip loop filter (LF). To compensate for leakage current in the LF, a leakage current compensation scheme is presented. With the leakage compensation scheme, the peak-to-peak jitter and rms jitter are 40ps and 7.62ps, respectively. The area of the LF was reduced by around a sixteenth part compared with a metal insulator metal (MIM) capacitor.
Keywords :
CMOS integrated circuits; MIM devices; MOS capacitors; flash memories; leakage currents; phase locked loops; CMOS technology; MIM capacitor; MOS capacitor; UFS system; fully integrated PLL; leakage current compensation; metal insulator metal capacitor; on-chip loop filter; peak-to-peak jitter; phase-locked loop; rms jitter; size 65 nm; time 40 ps; time 7.62 ps; universal flash storage system; CMOS integrated circuits; CMOS technology; Jitter; Leakage currents; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; Fully integrated PLL; Leakage compensation; Leakage current; MOS capacitor; Phase-locked loops; UFS;
Conference_Titel :
Consumer Electronics (ICCE), 2015 IEEE International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4799-7542-6
DOI :
10.1109/ICCE.2015.7066538
