Title :
Analysis of bridging defects in sequential CMOS circuits and their current testability
Author :
Rodriguez-Montanes, R. ; Figueras, J.
Author_Institution :
Dept. d´´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain
fDate :
28 Feb-3 Mar 1994
Abstract :
Differences between controllability conditions for IDDQ detectability iy in CMOS combinational and sequential circuits with bridging defects are presented. The usual detectability condition for current testability of bridges in combinational circuits is shown to fail for defective sequential circuits. A special class of bridges involving memory elements may change the state memorized in the element becoming current undetectable. Conditions for their occurrence have been investigated and their dependence on transistor size ratio and bridge resistance analyzed. A typical scan cell has been studied and its realistic bridges modifying the memorized state, identified
Keywords :
CMOS integrated circuits; combinatorial circuits; flip-flops; integrated logic circuits; logic testing; sequential circuits; CMOS combinational circuits; IDDQ detectability; bridge resistance; bridging defects; controllability conditions; current testability; detectability condition; flip flop; memorized state; memory elements; scan cell; scan path circuit; sequential CMOS circuits; state modifying topology; transistor size ratio; Bridge circuits; CMOS memory circuits; CMOS technology; Circuit faults; Circuit testing; Combinational circuits; Controllability; Feedback amplifiers; Sequential analysis; Sequential circuits;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326852
