Title :
Taking advantage of high level functional information to refine timing analysis and timing information
Author :
Safinia, C. ; Leveugle, R. ; Saucier, G.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
fDate :
28 Feb-3 Mar 1994
Abstract :
High level functional information, available in a circuit specification, can be used to refine timing analysis or modeling. The notion of functional false path is first introduced. Then, the principles of an accurate timing analysis are presented for circuits made up of a controller and a datapath. The approach takes advantage of the circuit hierarchy to reduce the computation complexity and avoids reporting functional false paths
Keywords :
computational complexity; logic CAD; logic design; circuit hierarchy; circuit specification; computation complexity; controller; datapath; functional false path; high level functional information; high level synthesis; minimum clock period; timing analysis; timing information; timing verification; Circuit simulation; Circuit synthesis; Computational modeling; Control system synthesis; High level synthesis; Independent component analysis; Information analysis; Integrated circuit interconnections; Performance analysis; Timing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326853
