2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Author

Hirano, H. ; Honda, T. ; Moriwaki, N. ; Nakakuma, T. ; Inoue, A. ; Nakane, G. ; Chaya, S. ; Sumi, T.

Author_Institution

Kyoto Res. Lab., Kyoto, Japan

fYear

1996

fDate

13-15 June 1996

Firstpage

48

Lastpage

49

Abstract

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

Keywords

cellular arrays; ferroelectric storage; memory architecture; microcontrollers; random-access storage; timing; 100 ns; 2 V; FeRAM; access time; bitline-driven read scheme; high speed operation; low voltage operation; memory architecture; microcontrollers; mobile information terminals; nonrelaxation reference cell; nonvolatile ferroelectric memory; Batteries; Capacitors; Ferroelectric films; Ferroelectric materials; Low voltage; Memory architecture; Microcontrollers; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507711

Filename

507711