DocumentCode
2124596
Title
The utilization of the electrical model synthesis technique for the MOS interface trap parameters measurement
Author
Baltianski, S. Sh
Author_Institution
Penza State Tech. Univ., Penza, Russia
Volume
2
fYear
1996
fDate
9-12 Oct 1996
Firstpage
549
Abstract
A method using the well-known conductance technique is developed. The basis of the approach is the representation of the approximate function as a rational form. This form allows the decomposition of the approximate function into elementary fractions, The extension of the energy range is provided and the error estimation carried out for the extracted interface trap parameters
Keywords
MIS devices; MIS structures; electron traps; equivalent circuits; hole traps; interface states; semiconductor device models; MOS interface trap parameters; approximate function; conductance technique; electrical model synthesis technique; error estimation; interface trap parameters measurement; rational form; Admittance; Capacitance; Data mining; Electric variables measurement; Equations; Equivalent circuits; Frequency; Tin;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 1996., International
Conference_Location
Sinaia
Print_ISBN
0-7803-3223-7
Type
conf
DOI
10.1109/SMICND.1996.557439
Filename
557439
Link To Document