Title :
Genesis: a behavioral synthesis system for hierarchical testability
Author :
Bhatia, Sandeep ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
Previous research in the area of behavioral synthesis of digital circuits has mostly concentrated on optimizing area and performance. We present a behavioral data path synthesis system, called Genesis, which is geared towards hierarchical testability. A test environment for each module in the data path is guaranteed during allocation such that it becomes possible to justify any desired test set at module inputs from system inputs, and propagate fault effects from module outputs to system outputs. Genesis provided 100% system-level testability for all the synthesized benchmarks with a three-to-four orders of magnitude improvement in test generation time as compared to an efficient gate-level sequential test generator. The area overhead of circuits synthesized by Genesis is usually zero over circuits synthesized by other behavioral synthesis systems which disregard testability. Genesis can also easily handle loop constructs in the behavioral specification
Keywords :
design for testability; directed graphs; logic CAD; logic testing; sequential circuits; C implementation; Genesis; area overhead; behavioral data path synthesis system; data flow graphs; hierarchical testability; loop constructs; module test environment; system-level testability; test generation time; test set justification; Benchmark testing; Circuit faults; Circuit synthesis; Circuit testing; Control system synthesis; Digital circuits; Integrated circuit interconnections; Registers; Sequential analysis; System testing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326865