• DocumentCode
    2124852
  • Title

    The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory

  • Author

    Fujisawa, H. ; Sakata, T. ; Sekiguchi, T. ; Nagashima, O. ; Kimura, K. ; Kajigaya, K.

  • Author_Institution
    Device Dev. Center, Hitachi Ltd., Tokyo, Japan
  • fYear
    1996
  • fDate
    13-15 June 1996
  • Firstpage
    50
  • Lastpage
    51
  • Abstract
    We have proposed the charge-share modified precharge-level architecture with self-timing precharge technique. It is a low-power dissipation architecture for achieving high-density, high-speed, and high-operating-margin simultaneously, making it a leading candidate for use in an Mb-scale ferroelectric memory.
  • Keywords
    ferroelectric storage; integrated memory circuits; memory architecture; timing; Mb-scale ferroelectric memory; charge-share modified precharge-level architecture; high-density memory; high-operating-margin; high-speed memory; low-power dissipation architecture; low-power ferroelectric memory; selective dataline activation; self-timing precharge technique; Ferroelectric materials;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-3339-X
  • Type

    conf

  • DOI
    10.1109/VLSIC.1996.507712
  • Filename
    507712
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2124852