Title :
Random testing of interconnects in a boundary scan environment
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fDate :
28 Feb-3 Mar 1994
Abstract :
In this paper, we propose a methodology for the random testing of interconnects with tri-state nets. A simple yet effective LFSR based impulse random test vector generator is designed to generate desired random vectors which will not activate multiple tri-state drivers with different values. The detail statistical analysis is conducted to derive two simple guidelines for the determination of test hardware configuration and the test length. The results show that the test length is compatible with the deterministic test methods
Keywords :
automatic test equipment; automatic testing; boundary scan testing; built-in self test; fault location; logic testing; printed circuit accessories; printed circuit testing; random processes; PCB testing; boundary scan environment; deterministic test; fault coverage analysis; impulse random test vector generator; interconnects; multiple tri-state drivers; random testing; short fault; statistical analysis; test hardware configuration; test length; tri-state nets; Automatic testing; Built-in self-test; Circuit testing; Hardware; Impulse testing; Integrated circuit interconnections; Pins; Statistical analysis; Surface-mount technology; Vectors;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326873
