Nondeterministic finite-state machines and sequential don´t cares

Author

Damiani, Maurizio

Author_Institution

Dipartimento di Elettronica e Inf., Padova Univ., Italy

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

192

Lastpage

198

Abstract

Nondeterministic finite-state machines are being considered for extracting and representing sequential don´t care conditions arising in high-level descriptions. This paper shows that they can also be used for capturing in full the sequential don´t cares arising from embedding of a machine in a larger synchronous network in a uniform way. A novel algorithm for synthesizing a minimum-state deterministic finite-state machine from a nondeterministic one is developed here. The techniques developed in this paper are useful when incorporated in a synthesis system extracting sequential don´t care information from high-level descriptions

Keywords

finite state machines; logic CAD; minimisation of switching nets; sequential switching; finite-state machines; high-level descriptions; machine embedding; minimum-state deterministic FSM; nondeterministic FSM; sequential don´t cares; synchronous network; synthesis system; Circuit synthesis; Combinational circuits; Hardware design languages; High level synthesis; Integrated circuit interconnections; Logic; Minimization; Network synthesis; Observability; Processor scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326877

Filename

326877