A hierarchical approach to fault collapsing

One central point of testing is the choice of the fault model and the faults which have to be considered to ensure the correct behaviour of a circuit. The number of faults has a strong influence on the costs which must be paid for in the generation of a test set. For logical fault models this number can be reduced using equivalence relations between faults. Since the complexity of digital circuits is increasing, hierarchical design is becoming more and more important. In this paper, we show that in the case of a hierarchical circuit description often more equivalence relations between faults can be recognized efficiently than in the case of a nonhierarchical description. With respect to the stuck-at fault model, our experiments show that the computation of these equivalence relations can be performed in negligible time and that the number of faults can be reduced considerably