Title :
Generating test patterns for bridge faults in CMOS ICs
Author :
Chess, Brian ; Larrabee, Tracy
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
We describe a system for generating accurate tests for bridge faults (with or without feedback) in CMOS ICs. We present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridge faults via topological analysis of the feedback-influenced region of the faulted circuit (without the need for any post-test verification or explicit examination of inversion parity). We describe our test pattern generation system´s treatment of feedback bridge faults in detail and report on the system´s performance
Keywords :
CMOS integrated circuits; feedback; integrated circuit testing; integrated logic circuits; logic testing; network topology; CMOS ICs; Test Guarantee Theorem; feedback bridge faults; test pattern generation; topological analysis; Bridge circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Feedback circuits; Logic functions; Semiconductor device modeling; Test pattern generators;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326881
