• DocumentCode
    2125270
  • Title

    A state space decomposition algorithm for approximate FSM traversal

  • Author

    Cho, Hyunwoo ; Hachtel, Gary D. ; Macii, Enrico ; Poncino, Massimo ; Somenzi, Fabio

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
  • fYear
    1994
  • fDate
    28 Feb-3 Mar 1994
  • Firstpage
    137
  • Lastpage
    141
  • Abstract
    Approximate FSM traversal is very useful in many applications of interest, when the size of the problem to be solved is too large to be handled by exact methods. The quality of the approximation strongly depends on how state variables are partitioned to decompose the state space, and exploiting circuit structure appears to be the most promising technique to determine a good state variable partition. In this paper we formulate the state space decomposition problem as a graph problem to be solved on the latch connection graph the FSM under investigation. Structural analysis on that graph is used to determine an initial partition; breaking and aggregation, based on seed generation, clustering, and iterative refinement of the current result, are then performed on the initial solution. Approximate FSM traversal results obtained on the largest ISCAS89 examples show the effectiveness of the proposed algorithm
  • Keywords
    VLSI; circuit CAD; directed graphs; finite state machines; logic CAD; sequential circuits; state-space methods; approximate FSM traversal; clustering; graph problem; iterative refinement; latch connection graph; seed generation; state space decomposition algorithm; state variable partition; structural analysis; Circuit synthesis; Circuit testing; Clustering algorithms; Counting circuits; Latches; Partitioning algorithms; Performance analysis; Reachability analysis; State-space methods; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
  • Conference_Location
    Paris
  • Print_ISBN
    0-8186-5410-4
  • Type

    conf

  • DOI
    10.1109/EDTC.1994.326885
  • Filename
    326885