A fragmented register architecture and test advisor for BIST

Author

Illman, R.J. ; Traynor, D.J.

Author_Institution

ICL Corporate Systems

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

124

Lastpage

129

Abstract

This paper describes two new developments in the implementation of quasi-exhaustive BIST. These are a new architecture, in which a conventional LFSR/MISR is broken down into three separate elements, and a CAD “test advisor” which provides a fast check of BIST DFT rules and informs the chip designer how to configure the registers and LFSRs within a design. These two new developments are closely interdependent and give a major increase in DFT productivity when implementing BIST

Keywords

application specific integrated circuits; built-in self test; combinatorial circuits; design for testability; logic CAD; logic testing; ASIC design; BIST DFT rules; CAD test advisor; DFT productivity; LFSR configuration; combinational logic; fragmented register architecture; logic partitioning; quasi-exhaustive BIST; register configuration; scan chain configuration; Automatic test pattern generation; Automatic testing; Built-in self-test; Design automation; Design for testability; Logic design; Productivity; Registers; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326887

Filename

326887