Title :
A fully integrated low noise RF frequency synthesizer design for mobile communication application
Author :
Seog-Jun Lee ; Beomsup Kim ; Kwyro Lee
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
A fully monolithic PLL frequency synthesizer circuit implemented in a 0.8 /spl mu/m CMOS technology is presented. The measured result shows a frequency range of 700 MHz to 1 GHz with -100 dBc/Hz phase noise at a 1 MHz carrier offset. The test chip consumes 125 mW at maximum frequency from a 5 V supply. No external components are used except a passive filter and supply decoupling capacitors.
Keywords :
CMOS analogue integrated circuits; frequency synthesizers; integrated circuit noise; land mobile radio; phase locked loops; phase noise; 0.8 micron; 125 mW; 5 V; 700 MHz to 1 GHz; CMOS chip; carrier offset; frequency range; integrated RF frequency synthesizer design; mobile communication; monolithic PLL circuit; passive filter; phase noise; supply decoupling capacitor; CMOS technology; Frequency measurement; Frequency synthesizers; Integrated circuit measurements; Integrated circuit technology; Noise measurement; Phase locked loops; Phase measurement; Radio frequency; Semiconductor device measurement;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507714
