Title :
Signature analysis for sequential circuits with reset
Author :
Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
fDate :
28 Feb-3 Mar 1994
Abstract :
When test responses are compacted, even some erroneous response sequences can lead to the error-free signature. This phenomenon of aliasing has been studied thoroughly using the assumption that errors in successive responses are statistically independent. In this paper signature analysis and aliasing are investigated for the test responses of sequential circuits with reset where errors can be correlated both in space and time. The probability of aliasing in a signature analyzer with an irreducible characteristic polynomial of degree k tends to 2-k as test lengths increase
Keywords :
built-in self test; error analysis; logic testing; probability; sequential circuits; BIST; aliasing; errors; irreducible characteristic polynomial; probability; reset; sequential circuits; signature analysis; test response compaction; Built-in self-test; Circuit analysis; Circuit faults; Circuit testing; Compaction; Computer errors; Probability; Registers; Sequential analysis; Sequential circuits;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326889
