DocumentCode
2125382
Title
A low cost BIST methodology and associated novel test pattern generator
Author
Lin, Sen-Pin ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
106
Lastpage
112
Abstract
The area overhead and performance degradation associated with the hardware used to make a circuit testable using the conventional BILBO methodology can often be excessive. This paper presents a new BILBO-oriented methodology, called Built-In test for Balanced Structure (BIBS), that significantly reduces the number of BILBO registers used in creating a testable circuit, and thus decreases the area overhead and performance degradation. The concept of k-step functionally testable circuits is introduced. When the BIBS methodology is employed, circuits under test are guaranteed to be 1-step functionally testable and thus a high fault coverage can be achieved. A novel test pattern generator design to achieve 1-step functional testability for the BIBS TDM is presented
Keywords
built-in self test; design for testability; logic design; logic testing; BILBO registers; BILBO-oriented methodology; Built-In test for Balanced Structure; area overhead; built-in self-test; high fault coverage; k-step functionally testable circuits; low cost BIST methodology; performance degradation; test pattern generator; Built-in self-test; Circuit faults; Circuit testing; Costs; Degradation; Kernel; Logic testing; Registers; Test pattern generators; Time division multiplexing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326890
Filename
326890
Link To Document