Title :
FPGA partitioning for critical paths
Author :
Brasen, Daniel ; Saucier, Gabride
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
fDate :
28 Feb-3 Mar 1994
Abstract :
FPGA packages have maximum size constraints much larger than the number of IO pins. The resulting IO bottleneck during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. This cuts more critical timing paths between packages and drastically decreases the circuit operational frequency. In this paper, a bottom-up circuit partitioning method with cone structures is presented. The solution can minimize the delay of critical paths that slow down the circuit without changing the number of partitioned packages
Keywords :
delays; logic CAD; logic arrays; FPGA packages; FPGA partitioning; bottom-up method; circuit partitioning; critical paths; delay minimisation; field programmable gate arrays; timing paths; Circuits; Clustering algorithms; Delay; Field programmable gate arrays; Iterative algorithms; Packaging; Partitioning algorithms; Pins; Timing; Wires;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326891
