Title :
Delay reduction by segment substitution
Author :
Ahuja, Hitesh ; Menon, P.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fDate :
28 Feb-3 Mar 1994
Abstract :
This paper presents a new algorithm for reducing the delay of combinational circuits by structural modifications. Delay reduction is obtained by substituting delay-inefficient segments of the longest path in the circuit, by faster segments which perform the same function. Experimental results with the ISCAS85 benchmark circuits showed good delay reduction with only moderate area increase. Extension of this method for delay reduction of technology-mapped circuits appears to be feasible
Keywords :
combinatorial circuits; delays; minimisation of switching nets; ISCAS85 benchmark circuits; area increase; combinational circuits; delay minimization; delay reduction; logic optimization; segment substitution; structural modifications; technology-mapped circuits; Circuit synthesis; Clocks; Combinational circuits; Delay; Integrated circuit interconnections; Logic circuits; Minimization methods; Optimization methods; Registers; Routing;
Conference_Titel :
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-5410-4
DOI :
10.1109/EDTC.1994.326894
