Title :
A cost-oriented two-port unified cache for low-power RISC microprocessors
Author :
Mizuno, H. ; Ishibashi, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
Inexpensive implementation of a two-ported unified cache by using a separated bit-line memory hierarchy architecture is proposed for low-cost microprocessor applications. The same bit-rate as with conventional separated caches can be realized while the size can be reduced by 40% with capacity of more than 64 KB. The cache is physically addressable and achieves 4.2 ns latency.
Keywords :
cache storage; memory architecture; microprocessor chips; reduced instruction set computing; two-port networks; 4.2 ns; 64 KB; bit rate; cost; latency; low-power RISC microprocessor; separated bit-line memory hierarchy architecture; size; two-port unified cache; Delay; Memory architecture; Microprocessors; Reduced instruction set computing;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507721
