Title :
A compact on-chip ECC for low cost flash memories
Author :
Tanzawa, T. ; Tanaka, T. ; Takeuchi, K. ; Shirota, R. ; Aritome, S. ; Watanabe, H. ; Hemink, G. ; Shimizu, K. ; Sato, S. ; Takeuchi, Y. ; Ohuchi, K.
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A compact on-chip Error Correcting Code/Circuit (ECC) for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64 M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 10/sup 6/ write/erase cycles.
Keywords :
EPROM; NAND circuits; error correction codes; integrated memory circuits; 64 Mbit; area overhead; chip size; compact on-chip ECC; cumulative sector error rate; error correcting code circuit; low cost NAND flash memory; random access time; reliability; Circuits; Costs; Error analysis; Error correction codes; Flash memory;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507722
