A high-resolution, compact, and low-power ADC suitable for multi-channel implementation: measurements and methods of self-calibration

Author

Jansson, C.

Author_Institution

Dept. of Sensor Technol., Nat. Defence Res. Establ., Linkoping, Sweden

fYear

1996

fDate

13-15 June 1996

Firstpage

92

Lastpage

93

Abstract

The first and promising measurements of a 16-bit ADC using a new topology for high-resolution and medium speed applications have been presented. The noise level was measured to 0.5 lsb and a conversion rate of 12.8 kHz verified. The core area of a single ADC channel is 40/spl times/1640 /spl mu/m/sup 2/ and the power consumption 0.5 mW. DNL and INL was measured to 1 bit and 5 bit, respectively, due to a non-optimum design. Easily implemented internal on-fly auto-calibration methods to neutralize matching inaccuracies are suggested.

Keywords

analogue-digital conversion; calibration; 0.5 mW; 12.8 kHz; 16 bit; DNL; EC-ADC; INL; circuit topology; conversion rate; core area; design; high-resolution compact low-power ADC; internal on-fly auto-calibration; medium speed applications; multi-channel ADC; noise level; power consumption; self-calibration; Energy consumption; Noise level; Noise measurement; Topology; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507726

Filename

507726