Low voltage high speed circuit designs for giga-bit DRAMs

Author

Lee, K.-C. ; Kim, C.-H. ; Yoo, D.-Y. ; Sim, J.-H. ; Lee, S.-B. ; Moon, B.-S. ; Kim, K.-Y. ; Kim, N.-J. ; Yoo, S.-M. ; Yoo, J.-H. ; Cho, S.-I.

Author_Institution

Memory Div., Samsung Electron. Co. Ltd., Kyungki, South Korea

fYear

1996

fDate

13-15 June 1996

Firstpage

104

Lastpage

105

Abstract

An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.

Keywords

CMOS memory circuits; DRAM chips; VLSI; integrated circuit design; 0.18 micron; 0.32 micron; 0.4 micron; 1.5 V; 16 Mbit; 22 mA; 28 ns; 70 ns; KrF; KrF lithography; TiSi/sub 2/; charge-amplifying boosted sensing scheme; cross-coupled current mirror control scheme; current sense amplifier; dynamic RAM; giga scale densities; giga-bit DRAMs; high speed circuit designs; low resistance TiSi/sub 2/ wordlines; low voltage circuit designs; twin-well CMOS process; CMOS process; Circuit synthesis; Lithography; Low voltage; Mirrors; Radio control; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3339-X

Type

conf

DOI

10.1109/VLSIC.1996.507731

Filename

507731