Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications

The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. However, the achievable performance to commensurate the actual potential of TLS is limited by the thread-management overhead. In this paper, we have exploited the run-time behavior of the performance-critical loops to minimize such overhead to improve the performance using embedded applications. We have shown that an average speedup of 2.4 is achievable on a 4-way machine which supports TLS, but has no special mechanism to predict the loop trip count. Then we have augmented the machine with the perfect knowledge of the loop trip count and obtained an average speedup of 2.6. Finally, we have incorporated a simple stride predictor to predict the loop trip count dynamically. The proposed predictor has an average prediction accuracy of 96% and the machine then yields an average speedup of 2.5 for the chosen applications.