Incorporating the controller effects during register transfer level synthesis

High level synthesis (HLS) has been mainly concerned with datapath synthesis of a digital system. Consequently, controller effects are often ignored when performing HLS tasks. However, the controller may sometimes have significant contributions to the overall system area and delay. Thus, it is necessary to incorporate the controller effects during HLS. Since control synthesis tools such as MISII are time consuming, it is not feasible to synthesize a controller netlist every time a high level design decision is made. As a result, it is necessary to estimate the controller contribution. As a first step towards a comprehensive prediction scheme, we present a simple yet effective controller estimation model which can be invoked during the register-transfer synthesis phase of HLS, which attempts to reflect the incremental effects of iterative RT level transformations on the controller area and delay. Our model has been bench-marked and found to efficiently account for the controller area and delay