Automatic synthesis of BISTed data paths from high level specification

Author

Flottes, M.L. ; Hammad, D. ; Rouzeyre, B.

Author_Institution

Lab. d´´Inf. de Robotique et de Microelectron., Montpellier Univ., France

fYear

1994

fDate

28 Feb-3 Mar 1994

Firstpage

591

Lastpage

598

Abstract

The incorporation of an on-line concurrent test method into high level synthesis of data-paths is addressed. Test vectors are propagated through all data-path resources during their idle times from built-in test patterns generators to response collectors. Testing is considered on the behavioral description. From the knowledge of resource idle times, a test flow graph is built up. Synthesis is then performed merging this graph and the normal control/data flow graph

Keywords

built-in self test; concurrent engineering; design for testability; logic CAD; BISTed data paths; automatic synthesis; behavioral description; built-in test pattern generators; control/data flow graph; data-path resources; high level specification; high level synthesis; idle times; on-line concurrent test method; response collectors; test flow graph; test vectors; Automatic control; Built-in self-test; Circuit synthesis; Circuit testing; Hardware; High level synthesis; Redundancy; Registers; Robotics and automation; Sequential analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-5410-4

Type

conf

DOI

10.1109/EDTC.1994.326917

Filename

326917