Title :
Capacitance coupled bus with negative delay circuit for high speed and low power (10 GB/s<500 mW) synchronous DRAMs
Author :
Yamada, T. ; Suzuki, T. ; Agata, M. ; Fujiwara, A. ; Fujita, T.
Author_Institution :
Dev. Dept., Matsushita Electron. Corp., Kyoto, Japan
Abstract :
Capacitance coupled Bus (CcBus) with Negative Delay Circuit (NDC) architecture for high speed and low power Synchronous DRAMs (SDRAMs) has been developed. Data path power consumption is reduced to 1/5 (25mW@200MB/s). Transfer delay time is reduced to 1/2 (0.8 ns). High band width (10 GB/s) and low power (<500 mW) can be achieved. This 500 mW power consumption/package is an empirical value maintaining pause time in useful range. This architecture can keep Fill Frequencies (FF) in valuable region in Gbit-SDRAMs.
Keywords :
DRAM chips; VLSI; delay circuits; integrated circuit design; 10 GB/s; 500 mW; SDRAMs; bandwidth; capacitance coupled bus; data path power consumption; empirical value; fill frequencies; high speed ICs; low power circuits; negative delay circuit; pause time; synchronous DRAMs; transfer delay time; Capacitance; Coupling circuits; Delay effects; Energy consumption; Frequency; Packaging;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507735
