Title :
A 4 Gsamples/s line-receiver in 0.8 /spl mu/m CMOS
Author :
Johansson, H.O. ; Jiren Yuan ; Svensson, C.
Author_Institution :
Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden
Abstract :
The interconnects between chips are gaining in importance. We study a line-receiver to find out what is the limit of transmission speed onto a CMOS chip. The high tracking-speed of an NMOS sampling switch is used together with parallelism to attain high data-rates. 4 Gsamples/s sample-rate and 2 Gbit/s bit-rate (two samples per bit) has been shown experimentally with a 0.8 /spl mu/m CMOS test-circuit. Single pulse measurements and simulations show that even higher rates are possible.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; packaging; receivers; wiring; 0.8 micron; 2 Gbit/s; CMOS; NMOS sampling switch; line-receiver; parallelism; single pulse measurements; tracking-speed; transmission speed; MOS devices; Pulse measurements; Sampling methods; Switches; Testing;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507736
