DocumentCode
2125949
Title
Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning
Author
Nedjah, Nadia ; Mourelle, Luiza DeMacedo
Author_Institution
State Univ. of Rio de Janeiro, Rio de Janeiro
fYear
2007
fDate
24-27 Oct. 2007
Firstpage
117
Lastpage
124
Abstract
Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which pre-processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the sliding- window method. The partitioning strategy used here allows variable-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. The implementation is efficient when compared against related existing hardware implementations.
Keywords
cryptography; digital arithmetic; cryptography; exponentiation process; modular exponentiation; modular multiplications; non-zero partitions; partitioning strategy; sliding-window method; variable-length partitioning; Computer architecture; Hardware; Heart; High performance computing; NP-complete problem; Partitioning algorithms; Public key cryptography; Systems engineering and theory; Telecommunication computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and High Performance Computing, 2007. SBAC-PAD 2007. 19th International Symposium on
Conference_Location
Rio Grande do Sul
ISSN
1550-6533
Print_ISBN
978-0-7695-3014-7
Type
conf
DOI
10.1109/SBAC-PAD.2007.28
Filename
4384049
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