DocumentCode
2126003
Title
Testability of circuits derived from functional decision diagrams
Author
Becker, Bernd ; Drechsler, Rolf
Author_Institution
Dept. of Comput. Sci., Johann Wolfgang Goethe Univ., Frankfurt, Germany
fYear
1994
fDate
28 Feb-3 Mar 1994
Firstpage
667
Abstract
We investigate the testability properties of Boolean networks derived from a special class of multi-level AND/EXOR expressions, called ordered functional decision diagrams (OFDDs). We consider the stuck-at fault model (SAFM) and the cellular fault model (CFM). All occurring redundancies are classified. The resulting circuits are highly testable with nearly 100% fault coverage on average
Keywords
Boolean functions; combinatorial circuits; controllability; logic testing; redundancy; Boolean networks; cellular fault model; fault coverage; multilevel AND/EXOR expressions; ordered functional decision diagrams; redundancies classification; stuck-at fault model; testability properties; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Controllability; Fault location; Inverters; Libraries; Packaging; Redundancy;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-5410-4
Type
conf
DOI
10.1109/EDTC.1994.326922
Filename
326922
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