Title :
A 700 Mbps/pin CMOS signalling interface using current integrating receivers
Author :
Sidiropoulos, S. ; Horowitz, M.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
A high speed CMOS signalling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes 1-V push-pull drivers, a Delay Line PLL and sampling of the data on both half-periods of the clock. In order to increase the noise immunity of the reception, current-integrating receivers are used to sample the data in the input pads. Chips fabricated in 0.8-/spl mu/m CMOS technology achieve transfer rates of 740 Mbits/sec/pin operating from a 3.3-V supply with a bit error rate of less than 10/sup -14/.
Keywords :
CMOS digital integrated circuits; integrating circuits; multiprocessor interconnection networks; receivers; telecommunication signalling; 0.8 micron; 3.3 V; 740 Mbit/s; bit error rate; current integrating receiver; data sampling; delay line PLL; high speed CMOS signalling interface; multiprocessor interconnection network; noise immunity; push-pull driver; Bit error rate; CMOS technology; Clocks; Delay lines; Multiprocessor interconnection networks; Phase locked loops; Sampling methods;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507747
