Title :
A 50% noise reduction interface using low-weight coding
Author :
Nakamura, K. ; Horowitz, M.A.
Author_Institution :
NEC Corp., Sagamihara, Japan
Abstract :
We have experimentally confirmed the theoretically predicted results of -50% noise reduction and -18% power reduction in an LSI interface. With a newly developed analog-MV circuit, delay time in encoding is less than 1-ns (>1 GHz), and layout-area for an 86 to 96 codec is 0.063 mm/sup 2/ in a 0.5 um process. Use of a "low-weight coding scheme" with our developed analog-MV circuits appears to be a promising approach to the achievement of GHz-class VLSI interfaces.
Keywords :
analogue integrated circuits; codecs; integrated circuit noise; large scale integration; 0.5 micron; 1 GHz; 1 ns; LSI interface; analog majority voter circuit; codec; delay time; layout area; low-weight coding; noise; power consumption; Circuits; Codecs; Delay effects; Encoding; Large scale integration; Noise reduction; Very large scale integration;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507748
