Multi-antenna WCDMA receiver design with CORDIC

In this paper, the architecture of a multi-antenna CDMA receiver that is realized with CORDIC processors is presented. With multiple antennas, the receiver has a good performance of BER (bit-error-rate) compared to RAKE receiver, and the hardware has nearly the same complexity as the RAKE receiver. The CORDIC structure using the shifting-addition operation instead of the complex multiplier is more feasible and flexible to realize WCDMA receiver with VLSI hardware architecture. For the WCDMA receiver, the FIR filter of the channel equalizer is also implemented with CORDIC so that the hardware complexity is reduced greatly. At last, the experiment results prove that the CDMA CORDIC receiver is good at both hardware efficiency and interference rejection.