DocumentCode
2126411
Title
A high speed programming scheme for multi-level NAND flash memory
Author
Young-Joon Choi ; Kang-Deog Suh ; Yong-Nam Koh ; Jong-Wook Park ; Ki-Jong Lee ; Yun-Jin Cho ; Byung-Hoon Suh
Author_Institution
Samsung Electron. Co. Ltd., Kiheung, South Korea
fYear
1996
fDate
13-15 June 1996
Firstpage
170
Lastpage
171
Abstract
A new scheme for page programming of multi-level NAND flash memory has been developed. It maintains the 528 byte page size of 32 Mb NAND flash memories with a high throughput of 0.5 MB/s. The circuitry has been successfully implemented into an experimental 128 Mb multi-level flash memory.
Keywords
EPROM; NAND circuits; PLD programming; integrated memory circuits; 0.5 MB/s; 128 Mbit; 32 Mbit; high speed programming scheme; multi-level NAND flash memory; page programming; Circuits; Flash memory; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507758
Filename
507758
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